Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize conduction power loss it is desirable that power MOSFETs have a low specific on-resistance, which is defined as the product of the on-resistance (Ron) of the MOSFET multiplied by the active die area (A) of the MOSFET (Ron*A). A trench-type MOSFET, as shown in the schematic cross-sectional view of a MOSFET 10 in FIG. 1, provides a low specific on-resistance because of its high packing density or number of cells per unit area. As the cell density increases, the associated capacitances, such as the gate-to-source capacitance (Cgs), the gate-to-drain capacitance (Cgd), and the drain-to-source capacitance (Cds), also increase. In many switching applications such as the synchronous buck dc-dc converters used in mobile products, MOSFETs with a breakdown voltage in the range of 12 to 30V are required to operate at switching frequencies approaching 1 MHz. Therefore, it is desirable to minimize the switching or dynamic power loss caused by these capacitances. The magnitudes of these capacitances are directly proportional to the gate charge (Qg), the gate-drain charge (Qgd), and output charge (Qoss). Furthermore, when these devices operate in the third quadrant, i.e. where the drain-body junction is forward-biased, charge is stored as a result of minority carrier injection, and this stored charge causes a delay in switching speed of the device. It is therefore critical that a MOSFET switch have a low reverse recovery charge (Qrr).
U.S. Pat. No. 6,710,403 to Sapp proposes a dual-trench power MOSFET, as shown in FIG. 2, with two deeper polysilicon-filled trenches 22 on either side of an active trench 24, to lower the levels of Ron, Cgs and Cgd. However, MOSFET 20 does not lower the reverse recovery charge Qrr and requires the fabrication of trenches having two different depths. Furthermore, in MOSFET 20 the deep and shallow trenches are not self-aligned, which causes variations in mesa widths and hence in breakdown voltages.
As the switching-speed requirements increase to 1 MHz and above, driven by new applications such as CPU voltage regulator module (VRM), power MOSFETs are becoming increasingly unable to operate with satisfactory efficiency performance and power loss. Therefore, there is a clear need for a power MOS transistor that has low gate charges Qg and Qgd, a low output charge Qoss and a low reverse-recovery charge Qrr, in addition to having a low specific on-resistance (Ron*A).